1. Field of the Invention
The present invention relates to integrated circuit memory devices and, in particular, to an integrated, non-volatile, reconfigurable data protection scheme for an electrically erasable programmable read only memory (EEPROM) device.
2. Discussion of the Prior Art
Conventional electronic data processing systems utilize storage devices, i.e., memory, for holding items of information which are to be used in or manipulated by the system. A memory comprises an array of locations for storing information items, generally referred to as "words", in the form of a plurality of digital bits, i.e. 1s or 0s. Each storage location in the array has an associated address which defines its position in the memory array. Access to that location for the purpose of writing in or reading out an information word is gained by specifying the proper address together with an instruction that identifies the operation to be performed at the specified address.
To ensure the protection of stored information, it is common to designate certain areas of the memory array or groups of storage locations within the array as having "protected" status and to provide means for limiting access to these protected areas or locations.
Protection schemes are available for external bulk memory, such electrostatic system memory or magnetic core memory, of the type usually associated with data processing systems.
For example, U.S. Pat. No. 3,264,615 issued to R. P. Case et al. on Aug. 2, 1966, discloses a data processing system having an addressable bulk memory, a register for holding a memory address field which consists of a plurality of address bits that are common to a group of addresses, and comparison circuitry for comparing the address field held in the register with memory addresses sought to be accessed. The comparison determines whether the address sought to be accessed contains the pattern specified by the field. Control circuitry signals a violation of a protected area in response to a predetermined result of the comparison. The control circuit can cause either an equal or an unequal comparison result to signal a violation. Thus, the address field may specify either a protected area or an unprotected area separating non-contiguous protected areas. Variation in the size of the protected area is accomplished by varying the number of address bits in the field which must be compared. A count register holding a value identifying the number of bits to be compared controls this process. The field register, count register and the circuitry for determining which comparison result will signal violation of a protected area are all subject to program control so that their contents and status may be altered at will.
U.S Pat. No. 3,573,855 issued to H. G. Cragon on Apr. 6, 1971, discloses a data processing system which is provided with a central processing unit that includes an arithmetic unit which is accessible to and from a thin film memory over buffer channels. The system is provided with registers for storing upper and lower memory limits for data to be read, data to be written and instructions to be fetched for execution. Comparison circuitry responds to a request from memory for comparing each memory request with the limits stored in the register file. The request for memory access is enabled only if the comparison indicates that the access is within the specified limits.
U.S. Pat. No. 3,742,458 issued to Inoue et al. on June 26, 1973, discloses an apparatus for flexible protection against overwriting and destruction of the contents of selected portions of memory. Each memory unit is assigned a unique memory address number which serves to identify the memory unit and instructions to write data into the memory. The addresses are segregated into ranges of numbers defining separate memory portions to be protected, with the numbers at the boundaries of the ranges being entered into registers which can be reset to flexibly determine the protected ranges. Thus, the memory device is separated into three different portions: one permitting free writing access to the memory units, one withholding all writing access to the memory units, and one being conditioned to grant or withhold writing access according to the setting of a device, such as a flip-flop, which can be arranged for manual or programmable control. Whenever an instruction to alter a memory unit arises, the associated address number is entered into a register and compared by means of digital comparators with the range boundary numbers in their registers. A gate then grants or withholds access to the memory unit in accordance with the comparison, thereby controlling the insertion of data into each memory unit and providing protection to selected portions of the memory device.
In the case of monolithic integrated circuit memory devices, Read-Only-Memories (ROMs) are considered to be fully data-protected because ROM programming is performed one time only during fabrication. That is, once programmed, there is no way that the user can alter the contents of the ROM. Ultraviolet Erasable Programmable ROMs (UVEPROMs) provide the user with the flexibility to change the contents of the memory. To alter the contents of a UVEPROM, however, it is first necessary to erase the entire memory using UV light and then reprogram it with the desired data pattern. Another type of ROM is the so-called Electrically Erasable ROM (EEPROM). This memory type provides in-system programming and, like other ROMs, is also nonvolatile.
As in the case of the bulk memory examples discussed above, the need for memory protection for monolithic memory devices arises when the user, after deciding on the final data pattern, wants to permanently store the contents in the memory. Both UVEPROMs and EEPROMs are vulnerable to intentional or accidental data modifications. Therefore, it would be highly desirable to have available some means for providing data security for these types of devices.